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4

IRS233(0,2)(D)(S&J)PbF

Recommended Operating Conditions

The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the

tested with all supplies biased at 15 V differential.

Note 2: Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to

the Application Information section of this datasheet for more details.

Note 3: CAO input pin is internally clamped with a 5.2 V zener diode.

Dynamic Electrical Characteristics

Symbol

Definition

Min Typ Max Units Test Conditions

Turn-on propagation delay

400

500

700

Turn-off propagation delay

400

500

700

Turn-on rise time

—

80

125

Turn-off fall time

—

35

55

ITRIP to output shutdown propagation delay

400

660

920

ITRIP blanking time

—

400

—

ITRIP to FAULT indication delay

350

550

870

Input filter time (all six inputs)

—

325

—

LIN1,2,3 to FAULT clear time (2330/2)

5300 8500 13700

1300 2000 3100

DT

Deadtime:

(IRS2330(D))

(IRS2332(D))

500

700

1100

—

—

400

MDT

Deadtime matching: :

(IRS2330(D))

(IRS2332(D))

—

—

140

without

external deadtime

MT

—

—

50

without

external deadtime

larger than DT

PM

Pulse width distortion

—

—

75

ns

PM input 10 s

NOTE: For high side PWM, HIN pulse width must be > 1.5 usec

Symbol

Definition

Min.

Max.

Units

High-side floating supply voltage

Static high-side floating offset voltage

600

Transient high-side floating offset voltage

-50 (Note2)

600

High-side floating output voltage

Low-side and Logic fixed supply voltage

10

20

Logic ground

-5

5

Low-side output voltage

0

Logic input voltage (HIN1,2,3, LIN1,2,3 & ITRIP)

FAULT output voltage

Operational amplifier output voltage

Operational amplifier inverting input voltage

V

Ambient temperature

-40

125

°C