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CAT28F001PA-90BT Datasheet(PDF) 8 Page - Catalyst Semiconductor |
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CAT28F001PA-90BT Datasheet(HTML) 8 Page - Catalyst Semiconductor |
8 / 18 page CAT28F001 8 Doc. No. 25071-00 2/98 F-1 READ OPERATIONS Read Mode The CAT28F001 memory can be read from any of its Blocks (Boot Block, Main Block or Parameter Block), Status Register and Signature Information by sending the Read Command Mode to the Command Register. CAT28F001 automatically resets to Read Array mode upon initial device power up or after exit from deep power down. A Read operation is performed with both CE and OE low and with RP and OE high. Vpp can be either high or low. The data retrieved from the I/O pins reflects the contents of the memory location correspond- ing to the state of the 17 address pins. The respective timing waveforms for the read operation are shown in Figure 3. Refer to the AC Read characteristics for specific timing parameters. Signature Mode The signature mode allows the user to identify the IC manufacturer and the type of the device while the device resides in the target system. This mode can be activated in either of two ways; through the conventional method of applying a high voltage (12V) to address pin A9 or by sending an instruction to the command register (see Write Operations). The conventional method is entered as a regular read mode by driving the CE and OE low (with WE high), and applying the required high voltage on address pin A9 while the other address line are held at VIL. A Read cycle from address 0000H retrieves the binary code for the IC manufacturer on outputs I/O7 to I/O0: Catalyst Code = 0011 0001 (31H) A Read cycle from address 0001H retrieves the binary code for the device on outputs I/O7 to I/O0: CAT28F001T = 1001 0100 (94H) CAT28F001B = 1001 0101 (95H) Standby Mode With CE at a logic-high level, the CAT28F001 is placed in a standby mode where most of the device circuitry is disabled, thereby substantially reducing power con- sumption. The outputs are placed in a high-impendance state independent of the OE status. Deep Power-Down When RP is at logic-low level, the CAT28F001 is placed in a Deep Power-Down mode where all the device circuitry are disabled, thereby reducing the power con- sumption to 0.25 µW. Figure 3. A.C. Timing for Read Operation 28F001 F05 ADDRESSES CE (E) OE (G) WE (W) DATA (I/O) HIGH-Z POWER UP STANDBY DEVICE AND ADDRESS SELECTION OUPUTS ENABLED DATA VALID STANDBY ADDRESS STABLE OUTPUT VALID tAVQV (tACC) tELQX (tLZ) tGLQX (tOLZ) tGLQV (tOE) tELQV (tCE) tOH tGHQZ (tDF) tEHQZ tAVAV (tRC) POWER DOWN HIGH-Z tPHQV (tPWH) RP (P) |
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