CAT28LV65

5

Preliminary

Doc. No. 25041-00 2/98

DEVICE

UNDER

TEST

Vcc

1.8 K

OUTPUT

CL INCLUDES JIG CAPACITANCE

1. 3K

INPUT PULSE LEVELS

REFERENCE POINTS

2.0 V

0.6 V

V

- 0.3 V

0.0 V

CC

Figure 2. A.C. Testing Load Circuit (example)

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) A write pulse of less than 20ns duration will not initiate a write cycle.

(4) Input rise and fall times (10% and 90%) < 10 ns.

28LV65 F07

28LV65-25

28LV65-30

28LV65-35

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Units

Write Cycle Time

5

5

5

ms

Address Setup Time

0

0

0

ns

Address Hold Time

100

100

100

ns

CE Setup Time

0

0

0

ns

CE Hold Time

0

0

0

ns

CE Pulse Time

150

150

150

ns

OE Setup Time

10

10

10

ns

OE Hold Time

10

10

10

ns

WE Pulse Width

150

150

150

ns

Data Setup Time

100

100

100

ns

Data Hold Time

0

0

0

ns

Write Inhibit Period After Power-up

5

10

5

10

5

10

ms

Byte Load Cycle Time

0.1

100

0.1

100

0.1

100

µs

WE Low to RDY/BSY Low

220

220

220

ns

A.C. CHARACTERISTICS, Write Cycle

28LV65 F05