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CAT24WC03P-1.8 Datasheet(PDF) 5 Page - Catalyst Semiconductor |
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CAT24WC03P-1.8 Datasheet(HTML) 5 Page - Catalyst Semiconductor |
5 / 8 page CAT24WC03/05/09/17 5 Doc. No. 25063-00 2/98 S-1 Preliminary for 24WC03. If only one 24WC03 is addressed on the bus, all three address pins (A0, A1, and A2) can be left floating or connected to VSS A total of four devices can be addressed on a single bus when using 24WC05 device. Only A1 and A2 address pins are used with this device. The A0 address pin is a no connect pin and can be tied to VSS or left floating. If only one 24WC05 is being addressed on the bus, the address pins (A1 and A2) can be left floating or con- nected to VSS. Only two devices can be cascaded when using 24WC09. The only address pin used with this device is A2. The A0 and A1address pins are no connect pins and can be tied to VSS or left floating. If only one 24WC09 is being addressed on the bus, the address pin (A2) can be left floating or connected to VSS. The 24WC17 is a stand alone device. In this case, all address pins (A0, A1and A2) are no connect pins and can be tied to VSS or left floating. WP: Write Protect If the WP pin is tied to VCC the upper half of memory array becomes Write Protected (READ only)(locations 80H to FFH for 24WC03, locations 100H to 1FFH for 24WC05, locations 200H to 3FFH for 24WC09, locations 400H to 7FFH for 24WC17). When the WP pin is tied to VSS or left floating normal read/write operations are allowed to the device. I2C BUS PROTOCOL The following defines the features of the I2C bus proto- col: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24WC03/05/09/17 monitor the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING The bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four Figure 4. Acknowledge Timing Figure 5. Slave Address Bits 5020 FHD F06 ACKNOWLEDGE 1 START SCL FROM MASTER 89 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER 1 0 1 0 A2 A1 A0 R/W 1 0 1 0 A2 A1 a8 R/W 1 0 1 0 A2 a9 a8 R/W 1 0 1 0 a10 a9 a8 R/W 24WC03 24WC05 24WC09 24WC17 * A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device. ** a8, a9 and a10 correspond to the address of the memory array address word. ***A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3). |
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