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CAT28LV65NI-30T Datasheet(PDF) 9 Page - Catalyst Semiconductor |
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CAT28LV65NI-30T Datasheet(HTML) 9 Page - Catalyst Semiconductor |
9 / 10 page CAT28LV65 9 Preliminary Doc. No. 25041-00 2/98 HARDWARE DATA PROTECTION The following is a list of hardware data protection fea- tures that are incorporated into the CAT28LV65. (1) VCC sense provides for write protection when VCC falls below 2.0V min. (2) A power on delay mechanism, tINIT (see AC charac- teristics), provides a 5 to 10 ms delay before a write sequence, after VCC has reached 2.40V min. (3) Write inhibit is activated by holding any one of OE low, CE high or WE high. (4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. SOFTWARE DATA PROTECTION The CAT28LV65 features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write can be performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28LV65 is in the standard operating mode). Figure 9. Write Sequence for Activating Software Data Protection Figure 10. Write Sequence for Deactivating Software Data Protection 5094 FHD F08 5094 FHD F09 SOFTWARE DATA PROTECTION ACTIVATED (12) WRITE DATA: XX WRITE LAST BYTE TO LAST ADDRESS TO ANY ADDRESS WRITE DATA: AA ADDRESS: 1555 WRITE DATA: 55 ADDRESS: 0AAA WRITE DATA: A0 ADDRESS: 1555 WRITE DATA: AA ADDRESS: 1555 WRITE DATA: 55 ADDRESS: 0AAA WRITE DATA: 80 ADDRESS: 1555 WRITE DATA: AA ADDRESS: 1555 WRITE DATA: 55 ADDRESS: 0AAA WRITE DATA: 20 ADDRESS: 1555 Note: (1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC Max., after SDP activation. (1) |
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