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BR93H46RF-2LB Datasheet(HTML) 15 Page - Rohm

Part No. BR93H46RF-2LB
Description  Serial EEPROM Series Industrial EEPROM 125℃ Operation Microwire BUS EEPROM (3-wire)
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Maker  ROHM [Rohm]
Homepage  http://www.rohm.com
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BR93H46RF-2LB Datasheet(HTML) 15 Page - Rohm

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Datasheet
Datasheet
15/25
www.rohm.com
TSZ22111・15・001
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ02201-0R1R0G100250-1-2
BR93H46RF-2LB
27.Feb.2014 Rev.002
4) Write Enable (WEN) / Disable (WDS) Cycle
○At power on, this IC is in Write Disable status by the internal RESET circuit. Before executing the WRITE command, it
is necessary to execute the Write Enable command first. And, once this command is executed, writing is valid unitl the
Write Disable command is executed or the power is turned off.
However, the READ command is valid regardless of
whether Write Enable / Disable command is executed. Input to SK after 6 clocks of this command is available by either
“H” or “L”, but be sure to input it.
○When the Write Enable command is executed after power on, Write Enable status gets in. When the Write Disable
command is executed then, the IC gets in Write Disable status as same as at power on, and then the WRITE command is
canceled thereafter in software manner. However, the READ command is still executable. In Write Enable status, even
when the WRITE command is input by mistake, writing will still continue. To prevent such a mistake, it is recommended to
execute the Write Disable command after the completion of each WRITE execution.
Application
1) Method to cancel each command
○READ
○WRITE, WRAL
Figure 34. READ Cancel Available Timing
Figure 35. WRITE, WRAL Cancel Available Timing
a:From start bit to 25th clock rise
Cancel by CS=“L”
b:25th clock rise and after
Cancellation is not available by any means. If Vcc is turned OFF in this area,
designated address data is not guaranteed, therefore write once again.
c:26th clock rise and after
Cancel by CS=“L”
However, when write is started in b area (CS is ended), cancellation is not
available by any means.
And when SK clock is input continuously, cancellation is not available.
Start bit
Ope code
Address
Data
1bit
2bit
6bit
16bit
Cancel is available in all areas in read mode.
●Method to cancel:cancel by CS =“L”
Start bit
Ope code
Address
Data
tE/W
a
1bit
2bit
6bit
16bit
C
b
SK
・Rise of 25th clock
D1
Enlarged figure
D0
DI
24
25
26
27
a
b
c
Note 1)
If VCC is turned OFF in this area,
designated address data is not guaranteed.
Therefore, it is recommended to execute
WRITE once again.
Note 2)
If CS is started at the same timing as that of
the SK rise, WRITE execution/cancel becomes
unstable.
Therefore, it is recommended to set CS
to “L” in SK=”L” area.
As for SK rise, recommended
timing is of tCSS/tCSH or higher.
CS
1
2
1
5
High-Z
0
0
SK
DI
DO
9
3
4
6
7
8
ENABLE=1
1
DISABLE=0
0
~~
~~
~~
~~
Figure 33. Write Enable (WEN) / Disable (WDS) Cycle


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