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BR93H46RF-2LB Datasheet(HTML) 21 Page - Rohm

Part No. BR93H46RF-2LB
Description  Serial EEPROM Series Industrial EEPROM 125℃ Operation Microwire BUS EEPROM (3-wire)
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Maker  ROHM [Rohm]
Homepage  http://www.rohm.com

BR93H46RF-2LB Datasheet(HTML) 21 Page - Rohm

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© 2013 ROHM Co., Ltd. All rights reserved.
27.Feb.2014 Rev.002
5) Power-Up/Down Conditions
・At power ON/OFF, set CS “L”.
When CS is “H”, this IC gets in input accept status (active). At power ON, set CS “L” to prevent malfunction from noise.
(When CS is in “L” status, all inputs are canceled.) At power decline low power status may prevail. Therefore, at power
OFF, set CS “L” to prevent malfunction from noise.
○POR circuit
This IC has a POR (Power On Reset) circuit as a mistake write countermeasure. After POR action, it gets in write disable
status. The POR circuit is valid only when power is ON, and does not work when power is OFF. However, if CS is “H” at
power ON/OFF, it may become write enable status owing to noises and the likes. For secure actions, observe the
following conditions.
1. Set CS=”L”
2. Turn on power so as to satisfy the recommended conditions of tR, tOFF, Vbot for POR circuit action.
○LVCC Circuit
LVCC (VCC-Lockout) circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ=1.9V) or below, it prevents data rewrite.
6) Noise Countermeasures
○VCC Noise (Bypass Capacitor)
When noise or surge gets in the power source line, malfunction may occur. Therefore, in removing these, it is
recommended to attach a bypass capacitor (0.1μF) between IC VCC and GND as close to IC as possible. It is also
recommended to attach a bypass capacitor between board VCC and GND.
○SK Noise
When the rise time (tR) of SK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock
bit displacement.
To avoid this, a Schmitt trigger circuit is built in SK input. The hysteresis width of this circuit is set about 0.2V. If noise
exists at SK input, set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise time (tR) of SK to 100ns
or below. In the case when the rise time is 100ns or higher, take sufficient noise countermeasures. Make the clock rise,
fall time as small as possible.
V bot
10m s or below
10m s or higher
0.3V or below
100m s or below 10m s or higher
0.2V or below
Bad example
Good example
Figure 50. Timing at Power ON/OFF
Figure 51. Rise Waveform Diagram
(Bad example)CS pin is pulled up to Vcc.
In this case, CS becomes “H” (active status), EEPROM may
malfunction or have write error due to noises. This is true even
when CS input is High-Z.
(Good example)It is “L” at power ON/OFF.
Set 10ms or higher to recharge at power OFF.
When power is turned on without observing this condition,
IC internal circuit may not be reset.
Recommended conditions of tR, tOFF,

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