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BU16501KS2 Datasheet(PDF) 8 Page - Rohm |
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BU16501KS2 Datasheet(HTML) 8 Page - Rohm |
8 / 32 page 8/29 Datasheet Datasheet BU16501KS2 © 2013 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 TSZ02201-0G3G0CZ00250-1-2 01.Oct.2013 Rev.001 Serial Interface 1. SPI format ・When IFMODE is set to “H”, it can interface with SPI format. ・The serial interface is four terminals (serial clock terminal (SCL), serial data input terminal (SDA), and chip selection input terminal (CE)). (1)Write operation ・ Data is taken into an internal shift register with rising edge of SCL. (Max of the frequency is 13MHz.) ・ The receive data becomes enable in the “H" section of CE. (Active “H".) ・ The transmit data is forwarded (with MSB-First) in the order of write command “0”(1bit), the control register address (7bit) and data (8bit). Figure 2. Writing format (2)Timing diagram Figure 3. Timing diagram (SPI format) 2. I 2C BUS format When IFMODE is set to “L”, it can interface with I 2C BUS format. (1) Slave address CE A7 A6 A5 A4 A3 A2 A1 R/W L 1 1 1 0 1 0 0 0 H 1 1 1 0 1 0 1 (2) Bit Transfer SCL transfers 1-bit data during H. During H of SCL, SDA cannot be changed at the time of bit transfer. If SDA changes while SCL is H, START conditions or STOP conditions will occur and it will be interpreted as a control signal. SDA SCL SDA a state of stability : Data are effective SDA It can change Figure 4. Bit transfer (I 2C format) CE SCL SDA W A6 A5 A4 A3 A2 A1 A0 D4 D3 D2 D1 D0 D7 D6 D5 twlc CE SCL SDA tcsw twhc tcss tscyc tss tsh tcgh |
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