DMOS Full-Bridge PWM Motor Driver

A3959

9

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

24

23

22

21

28

27

26

25

20

17

16

15

NC

SENSE

SLEEP

NO

CONNECTION

NC

LOAD SUPPLY

NC

NO

CONNECTION

EXT MODE

REF

V

REG

1

2

3

4

5

8

9

12

11

14

13

10

GROUND

GROUND

GROUND

CP

PHASE

NC

NC

ENABLE

BLANK

LOGIC SUPPLY

ROSC

NC

NC

6

7

19

18

Terminal List

PWM TIMER

÷10

24

23

22

21

20

19

18

17

16

15

14

13

GROUND

GROUND

SLEEP

LOAD

SUPPLY

SENSE

EXT MODE

REF

Dwg. PP-069-5A

1

2

3

4

5

6

7

8

9

12

11

10

9

GROUND

GROUND

CP

PHASE

LOGIC

SUPPLY

ENABLE

BLANK

ı θ

ROSC

CHARGE PUMP

GROUND

GROUND

24

23

22

21

20

17

16

15

14

13

GROUND

GROUND

SLEEP

NO

CONNECTION

LOAD SUPPLY

SENSE

NO

CONNECTION

EXT MODE

REF

Dwg. PP-069-4

1

2

3

4

5

8

9

12

11

10

GROUND

GROUND

CP

PHASE

ENABLE

BLANK

LOGIC SUPPLY

ROSC

NC

NC

6

7

19

18

Terminal Name

Terminal Description

B (DIP)

LB (SOIC)

LP (TSSOP)

CP

Reservoir capacitor (typically 0.22 μF)

24

1

1

CP1 & CP2

The charge pump capacitor (typically 0.22 μF)

1 & 2

2 & 3

2 & 3

NC

No (internal) connection

—

—

4

PHASE

Logic input for direction control

3

4

5

ROSC

Oscillator resistor

4

5

6

GROUND

Grounds

5, 6, 7, 8*

6, 7

7, 8*

LOGIC SUPPLY

VDD, the low voltage (typically 5 V) supply

9

8

9

ENABLE

Logic input for enable control

10

9

10

NC

No (internal) connection

–

–

11

PFD2

Logic-level input for fast decay

11

10

12

BLANK

Logic-level input for blanking control

12

11

13

PFD1

Logic-level input for fast decay

13

12

14

REF

VREF, the load current reference input voltage

14

13

15

EXT MODE

Logic input for PWM mode control

15

14

16

NO CONNECT

No (Internal) connection

—

15

17

OUTA

One of two DMOS bridge outputs to the motor

16

16

18

NC

No (internal) connection

–

–

19, 20

SENSE

Sense resistor

17

17

21

NC

No (internal) connection

–

–

22

GROUND

Grounds

18, 19*

18, 19

—

LOAD SUPPLY

VBB, the high-current, 9.5 V to 50 V, motor supply

20

20

23

OUTB

One of two DMOS bridge outputs to the motor

21

21

24

NO CONNECT

No (Internal) connection

—

22

25

SLEEP

Logic-level Input for sleep operation

22

23

26

VREG

Regulator decoupling capacitor (typically 0.22 μF)

23

24

27

GROUND

Ground

—

—

28*

* For the B (DIP) package only, there is an indeterminate resistance between the substrate grounds (pins 6, 7, 18, and 19) and the grounds at pins 5

and 8. Pins 5 and 8, and 6, 7, 18, or 19 must be connected together externally. For the LP (TSSOP) package, the grounds at terminals 7, 8, and 28

should be connected together at the exposed pad beneath the device.