Serial-Input Constant-Current Latched LED Driver

with Open LED Detection and Dot Correction

A6275

6

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

TIMING REQUIREMENTS and SPECIFICATIONS

Serial data present at the input is transferred to the shift

register on the logic 0-to-logic 1 transition of the CLOCK input

pulse. On succeeding CLOCK pulses, the registers shift data in-

formation towards the SERIAL DATA OUTPUT. The serial data

must appear at the input prior to the rising edge of the CLOCK

input waveform.

Information present at any register is transferred to the

respective latch when the LATCH ENABLE is high (serial-to-

s

a

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.

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.

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L

B

A

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H

C

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a

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the latches are bypassed (LATCH ENABLE tied high) will

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data entry.

When the OUTPUT ENABLE input is high, the output sink

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.

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is not affected by the OUTPUT ENABLE input. With the OUT-

PUT ENABLE input low, the outputs are controlled by the state

.

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o

A. Data Active Time Before Clock Pulse

B. Data Active Time After Clock Pulse

D.

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C

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B

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NOTE: Timing is representative of a 10 MHz clock. Sig-

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CLOCK

SERIAL

DATA IN

LATCH

ENABLE

OUTPUT

ENABLE

Dwg. WP-029-1

50%

SERIAL

DATA OUT

DATA

DATA

50%

50%

50%

C

A

B

D

E

LOW = ALL OUTPUTS ENABLED

p

t

DATA

50%

p

t

LOW = OUTPUT ON

HIGH = OUTPUT OFF

OUTPUT

ENABLE

Dwg. WP-030-1A

DATA

10%

50%

pHL

t

pLH

t

HIGH = ALL OUTPUTS DISABLED (BLANKED)

f

t

r

t

90%

F

50%