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A6275SLWTR-T Datasheet(PDF) 7 Page - Allegro MicroSystems |
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A6275SLWTR-T Datasheet(HTML) 7 Page - Allegro MicroSystems |
7 / 12 page Serial-Input Constant-Current Latched LED Driver with Open LED Detection and Dot Correction A6275 6 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) Serial data present at the input is transferred to the shift register on the logic 0-to-logic 1 transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data in- formation towards the SERIAL DATA OUTPUT. The serial data must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the LATCH ENABLE is high (serial-to- s a a t a d w e n t p e c c a o t e u n i t n o c s e h c t a l e h T . ) n o i s r e v n o c l e l l a r a p e r e h w s n o i t a c i l p p A . h g i h d l e h s i E L B A N E H C T A L e h t s a g n o l the latches are bypassed (LATCH ENABLE tied high) will l a i r e s g n i r u d h g i h e b t u p n i E L B A N E T U P T U O e h t t a h t e r i u q e r data entry. When the OUTPUT ENABLE input is high, the output sink s e h c t a l e h t n i d e r o t s n o i t a m r o f n i e h T . ) F F O ( d e l b a s i d e r a s r e v i r d is not affected by the OUTPUT ENABLE input. With the OUT- PUT ENABLE input low, the outputs are controlled by the state . s e h c t a l e v i t c e p s e r r i e h t f o A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) ............................. 50 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) ................................. 20 ns C. Clock Pulse Width, tw(CK) .................................. 50 ns D. n o i t a v i t c A k c o l C n e e w t e B e m i T and Latch Enable, tsu(L) ............................... 100 ns E. Latch Enable Pulse Width, tw(L) ...................... 100 ns F. Output Enable Pulse Width, tw(OE) ................... 4.5 s NOTE: Timing is representative of a 10 MHz clock. Sig- . e l b a n i a t t a e r a s d e e p s r e h g i h y l t n a c i f i n Max. Clock Transition Time, tr or tf ....................... 10 s CLOCK SERIAL DATA IN LATCH ENABLE OUTPUT ENABLE OUTN Dwg. WP-029-1 50% SERIAL DATA OUT DATA DATA 50% 50% 50% C A B D E LOW = ALL OUTPUTS ENABLED p t DATA 50% p t LOW = OUTPUT ON HIGH = OUTPUT OFF OUTPUT ENABLE OUTN Dwg. WP-030-1A DATA 10% 50% pHL t pLH t HIGH = ALL OUTPUTS DISABLED (BLANKED) f t r t 90% F 50% |
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