Electronic Components Datasheet Search |
|
CS4362 Datasheet(PDF) 11 Page - Cirrus Logic |
|
CS4362 Datasheet(HTML) 11 Page - Cirrus Logic |
11 / 40 page CS4362 11 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT (For KQ TA =-10 to +70 °C; For BQ TA =-40 to +85 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1= VLC, CL =30pF) Notes: 23. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 24. Data must be held for sufficient time to bridge the transition time of CCLK. 25. For FSCK <1MHz. Parameter Symbol Min Max Unit CCLK Clock Frequency fsclk -MHz RST Rising Edge to CS Falling tsrs 500 - ns CCLK Edge to CS Falling (Note 23) tspi 500 - ns CS High Time Between Transmissions tcsh 1.0 - µs CS Falling to CCLK Edge tcss 20 - ns CCLK Low Time tscl -ns CCLK High Time tsch -ns CDIN to CCLK Rising Setup Time tdsu 40 - ns CCLK Rising to DATA Hold Time (Note 24) tdh 15 - ns Rise Time of CCLK and CDIN (Note 25) tr2 - 100 ns Fall Time of CCLK and CDIN (Note 25) tf2 - 100 ns MCLK 2 ------------------ 1 MCLK ------------------ 1 MCLK ------------------ t r2 t f2 t dsu t dh t sch t scl CS CC L K CD IN t css t csh t spi t srs RS T Figure 4. Control Port Timing - SPI Format |
Similar Part No. - CS4362 |
|
Similar Description - CS4362 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |