Electronic Components Datasheet Search |
|
CDB4812 Datasheet(PDF) 9 Page - Cirrus Logic |
|
CDB4812 Datasheet(HTML) 9 Page - Cirrus Logic |
9 / 36 page CS4812 DS291PP3 9 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MASTER (TA = 25°C, VA, VD = 5V; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30 pF) Notes: 15. Depending on the input clock configuration, CCLK may be up to 2*Fs temporarily during AutoBoot after RST is de-asserted and before the control port registers have been initialized. 16. Measured with a 2.2 k Ω pull-up resistor to VD. Parameter Symbol Min Typ Max Units SPI Master (AutoBoot) Mode (SPI/I2C = 0, SCPM/S = 1, Note 14) CCLK Clock Frequency (Note 15) fsck -Fs - kHz CCLK Low Time tscl -1/(2*Fs)- ns CCLK High Time tsch -1/(2*Fs)- ns CCLK Rise Time (Note 16) tr2 -12 - ns CCLK Fall Time (Note 16) tf2 -12 - ns RST rising to CS falling tsrs -42 - µs CS High Time Between Transmissions tcsh 37 - - µs CS Falling to CCLK Edge tcss 5- - µs CS Falling to CDOUT valid tdv - - 50 ns CCLK Falling to CDOUT valid tpd -- 100 ns CDIN to CCLK Rising Setup Time tdsu 80 - - ns CCLK Rising to DATA Hold Time tdh 80 - - ns CCLK Falling to CS rising tclcs 40 - - ns t r2 t f2 t dsu t dh t sch t scl CS CCLK CDIN t css t csh t clcs t srs RST t pd CDOUT t dv Figure 2. SPI Control Port Master Mode (AutoBoot) Timing |
Similar Part No. - CDB4812 |
|
Similar Description - CDB4812 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |