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W40S11-02 Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # W40S11-02
Description  SDRAM Buffer - 2 DIMM (Mobile)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

W40S11-02 Datasheet(HTML) 1 Page - Cypress Semiconductor

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SDRAM Buffer - 2 DIMM (Mobile)
W40S11-02
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
September 29, 1999, rev. **
Features
• Ten skew-controlled CMOS outputs (SDRAM0:9)
• Supports two SDRAM DIMMs
• Ideal for high-performance systems designed around
Intel®’s latest Mobile chip set
•I2C Serial configuration interface
• Skew between any two outputs is less than 250 ps
• 1 to 5 ns propagation delay
• DC to 133-MHz operation
• Single 3.3V supply voltage
• Low power CMOS design packaged in a 28-pin, 209-mil
SSOP (Shrink Small Outline Package)
Overview
The Cypress W40S11-02 is a low-voltage, ten-output clock
buffer. Output buffer impedance is approximately 15
Ω, which
is ideal for driving SDRAM DIMMs.
Key Specifications
Supply Voltages:........................................... VDD = 3.3V±5%
Operating Temperature:.................................... 0°C to +70°C
Input Threshold: .................................................. 1.5V typical
Maximum Input Voltage: .......................................VDD + 0.5V
Input Frequency:............................................... 0 to 133 MHz
BUF_IN to SDRAM0:9 Propagation Delay: ........1.0 to 5.0 ns
Output Edge Rate:................................................. >1.5 V/ns
Output Skew: ............................................................ ±250 ps
Output Duty Cycle: .................................. 45/55% worst case
Output Impedance: ........................................15 ohms typical
Output Type: ................................................ CMOS rail-to-rail
Intel is a registered trademark of Intel Corporation.
Pin Configuration
Block Diagram
Note:
1.
Internal pull-up resistor of 250K on SDATA, SCLOCK, and OE
inputs (should not be relied upon for pulling up to VDD).
[1]
[1]
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM0
Serial Port
SCLOCK
SDATA
Device Control
BUF_IN
OE
VDD
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
GND
BUF_IN
VDD
SDRAM8
GND
VDD
SDATA
VDD
SDRAM7
SDRAM6
GND
VDD
SDRAM5
SDRAM4
GND
OE
VDD
SDRAM9
GND
GND
SCLOCK
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
[1]


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