W48S101-04
PRELIMINARY
10
PCI Clock Outputs, PCI1:7 and PCI_F (Lump Capacitance Test Load = 30 pF
Parameter
Description
Test Condition/Comments
CPU = 66.8/100 MHz
Unit
Min.
Typ.
Max.
tP
Period
Measured on rising edge at 1.5V
30
ns
tH
High Time
Duration of clock cycle above 2.4V
12
ns
tL
Low Time
Duration of clock cycle below 0.4V
12
ns
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
250
ps
tSK
Output Skew
Measured on rising edge at 1.5V
500
ps
tO
CPU to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
1.5
4
ns
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
30
Ω
APIC0:1 Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.8/100 MHz
Unit
Min.
Typ.
Max.
f
Frequency, Actual
Frequency generated by crystal oscillator
14.31818
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.0V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.25V
45
55
%
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
1.5
ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
15
Ω
REF0:2 Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.8/100 MHz
Unit
Min.
Typ.
Max.
f
Frequency, Actual
Frequency generated by crystal oscillator
14.318
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
fST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
40
Ω
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