W48S87-04
PRELIMINARY
3
REF0/CPU3.3#_2.5
2
I/O
Fixed 14.318-MHz Output 0 and CPU Output Voltage Swing Selection
Input: As an output, this pin is used for various system applications. Output
voltage swing is controlled by voltage applied to VDD1. REF0 is stronger than
REF1 and should be used for driving ISA slots.
When an input, this pin selects the CPU clock output buffer characteristics that
are optimized for either 3.3V or 2.5V operation.
CPU3.3#_2.5
VDDQ2 Voltage (CPU0:3 Swing)
03.3V
12.5V
This input adjusts CPU clock output impedance so that a nominal 20
Ω output
impedance is maintained. This eliminates or reduces the need to adjust exter-
nal clock tuning components when changing VDDL2 voltage. CPU clock phase
is also adjusted so that both CPU and SDRAM and CPU-to-PCI clock skew is
maintained over the two VDDL2 voltage options. This input does not adjust
IOAPIC clock output characteristics.
REF1(CPU_Stop#)
46
I/O
Fixed 14.318-MHz Output 0 or CPU Clock Output Stop Control: Used for
various system applications. Output voltage swing is controlled by voltage ap-
plied to VDD1. REF0 is stronger than REF1 and should be used for driving ISA
slots.
If programmed as an input (refer to MODE pin description), this pin is used for
stopping the CPU clock outputs. When brought LOW, clock outputs CPU0:3
are stopped LOW after completing a full clock cycle (2–3 CPU clock latency).
When brought HIGH, clock outputs CPU0:3 are starting beginning with a full
clock cycle (2–3 CPU clock latency).
X1
4
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection
or as an external reference frequency input.
X2
5
I
Crystal Connection: An input connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
SDATA
23
I
Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
SCLOCK
24
I
Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
VDD1
1
P
Power Connection: Power supply for crystal oscillator and REF0:1 output
buffers. Connected to 3.3V supply.
VDD2
6,14
P
Power Connection: Power supply for PCI clock output buffers. Connected to
3.3V supply.
VDDL1
48
P
Power Connection: Power supply for IOAPIC output buffer. Connected to 2.5V
or 3.3V supply.
VDDL2
42
P
Power Connection: Power supply for CPU clock output buffers. Connected to
2.5V or 3.3V supply.
VDD3
19, 30, 36
P
Power Connection: Power supply for SDRAM clock output buffers. Connected
to 3.3V supply.
GND
3, 9, 16, 22,
27, 33, 39,
45
G
Ground Connection: Connect all ground pins to the common system ground
plane.
Pin Definitions (continued)
Pin Name
Pin
No.
Pin
Type
Pin Description
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