DS1673

8 of 20

EXTERNAL SRAM INTERFACE (WORD-WIDE) TO THE DS1673 Figure 4

MICROPROCESSOR MONITOR

The DS1673 monitors three vital conditions for a microprocessor: power supply, software execution, and

external override.

When an out-of-tolerance condition occurs, an internal power-fail signal is generated which forces the

RST

pin to the active state, thus warning a processor-based system of impending power failure. When

250 ms (typical) to allow the power supply and microprocessor to stabilize. Note, however, that if the

EOSC

bit is set to a logic 1 (to disable the oscillator during battery back-up mode), the reset signal will be

kept in an active state for 250 ms plus the start-up time of the oscillator.

The second monitoring function is push-button reset control. The DS1673 provides for a pushbutton

low for 250 ms.

The third microprocessor monitoring function provided by the DS1673 is a watchdog timer.

The

predetermined time period. The time period is set by the Time Delay (TD) bits in the Watchdog Register.

The time delay can be set to 250 ms, 500 ms, or 1000 ms (see Figure 5). If TD0 and TD1 are both set to

zero, the watchdog timer is disabled. When enabled, the watchdog timer starts timing out from the set

1000 ms time delay.

watchdog timer is reset and begins to time-out again. If the watchdog timer is allowed to time-out, then

microprocessor address signals, data signals, and/or control signals. To guarantee that the watchdog

timer does not time-out, a high-to-low transition must occur at or less than the minimum period.