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DS18S20 Datasheet(PDF) 6 Page - Dallas Semiconductor |
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DS18S20 Datasheet(HTML) 6 Page - Dallas Semiconductor |
6 / 27 page DS18S20 6 of 27 the alarm flag is set, the DS18S20 will respond to the alarm search command. This allows many DS18S20s to be connected in parallel doing simultaneous temperature measurements. If somewhere the temperature exceeds the limits, the alarming device(s) can be identified and read immediately without having to read non–alarming devices. 64-BIT LASERED ROM Each DS18S20 contains a unique ROM code that is 64–bits long. The first 8 bits are a 1–Wire family code (DS18S20 code is 10h). The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 4.) The 64–bit ROM and ROM Function Control section allow the DS18S20 to operate as a 1–Wire device and follow the 1–Wire protocol detailed in the section “1–Wire Bus System.” The functions required to control sections of the DS18S20 are not accessible until the ROM function protocol has been satisfied. This protocol is described in the ROM function protocol flowchart (Figure 5). The 1–Wire bus master must first provide one of five ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, or 5) Alarm Search. After a ROM functions sequence has been successfully executed, the functions specific to the DS18S20 are accessible and the bus master may then provide one of the six memory and control function commands. CRC GENERATION The DS18S20 has an 8–bit CRC stored in the most significant byte of the 64–bit ROM. The bus master can compute a CRC value from the first 56–bits of the 64–bit ROM and compare it to the value stored within the DS18S20 to determine if the ROM data has been received error–free by the bus master. The equivalent polynomial function of this CRC is: CRC = X 8 + X5 + X4 + 1 The DS18S20 also generates an 8–bit CRC value using the same polynomial function shown above and provides this value to the bus master to validate the transfer of data bytes. In each case where a CRC is used for data transfer validation, the bus master must calculate a CRC value using the polynomial function given above and compare the calculated value to either the 8–bit CRC value stored in the 64–bit ROM portion of the DS18S20 (for ROM reads) or the 8–bit CRC value computed within the DS18S20 (which is read as a ninth byte when the scratchpad is read). The comparison of CRC values and decision to continue with an operation are determined entirely by the bus master. There is no circuitry inside the DS18S20 that prevents a command sequence from proceeding if the CRC stored in or calculated by the DS18S20 does not match the value generated by the bus master. The 1–Wire CRC can be generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 6. Additional information about the Dallas 1–Wire Cyclic Redundancy Check is available in Application Note 27 entitled “Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor Touch Memory Products.” The shift register bits are initialized to “0”. Then starting with the least significant bit of the family code, one bit at a time is shifted in. After the eighth bit of the family code has been entered, then the serial number is entered. After the 48 th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC should return the shift register to all “0s”. 64-BIT LASERED ROM Figure 4 8-BIT CRC CODE 48-BIT SERIAL NUMBER 8-BIT FAMILY CODE (10h) MSB MSB LSB LSB LSB MSB |
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