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EP2AGX260EF29I3N Datasheet(PDF) 23 Page - Altera Corporation |
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EP2AGX260EF29I3N Datasheet(HTML) 23 Page - Altera Corporation |
23 / 78 page fixedclk clock frequency PCIe Receiver Detect — 125 — — 125 — — 125 — — 125 — MHz reconfig_ clk clock frequency Dynamic reconfig. clock frequency 2.5/ 37.5 (4) —50 2.5/ 37.5 (4) —50 2.5/ 37.5 (4) —50 2.5/ 37.5 (4) —50 MHz Delta time between reconfig_ clks (5) —— — 2 — — 2 — — 2 — — 2 ms Transceiver block minimum power-down pulse width —— 1 — — 1 — — 1 — — 1 — µs Receiver Supported I/O Standards 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, 2.5-V PCML, LVPECL, and LVDS Data rate (13) — 600 — 6375 600 — 3750 600 — 3750 600 — 3125 Mbps Absolute VMAX for a receiver pin (6) — — — 1.5 — — 1.5 — — 1.5 — — 1.5 V Absolute VMIN for a receiver pin — -0.4 — — -0.4 — — -0.4 — — -0.4 — — V Maximum peak-to-peak differential input voltage VID (diff p-p) VICM = 0.82 V setting — — 2.7 — — 2.7 — — 2.7 — — 2.7 V VICM =1.1 V setting (7) — — 1.6 — — 1.6 — — 1.6 — — 1.6 V Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 3 of 7) Symbol/ Description Condition I3 C4 C5 and I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max |
Similar Part No. - EP2AGX260EF29I3N |
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