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LPC1518JBD100 Datasheet(PDF) 21 Page - NXP Semiconductors |
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LPC1518JBD100 Datasheet(HTML) 21 Page - NXP Semiconductors |
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21 / 99 page  LPC15XX All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved. Product data sheet Rev. 1 — 19 February 2014 21 of 99 NXP Semiconductors LPC15xx 32-bit ARM Cortex-M3 microcontroller 8. Functional description 8.1 ARM Cortex-M3 processor The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware division, hardware single-cycle multiply, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual, which is available on the official ARM website. 8.2 Memory Protection Unit (MPU) The LPC15xx have a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to eight regions each of which can be divided into eight subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place. PIO1_12 - - 9 SCT0 input mux PIO1_13 - - 11 SCT0 input mux PIO1_15 - - 12 SCT1 input mux PIO1_16 - - 18 SCT1 input mux PIO1_18 - - 25 SCT2 input mux PIO1_19 - - 29 SCT2 input mux PIO1_21 - - 37 SCT3 input mux PIO1_22 - - 38 SCT3 input mux PIO1_26 - - 48 SCTIPU input SAMPLE_IN_A3 PIO1_27 - - 50 FREQMEAS Table 5. Pins connected to the INPUT MUX and SCT IPU Symbol Description |
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