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LPC1518JBD100 Datasheet(PDF) 43 Page - NXP Semiconductors |
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LPC1518JBD100 Datasheet(HTML) 43 Page - NXP Semiconductors |
43 / 99 page LPC15XX All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved. Product data sheet Rev. 1 — 19 February 2014 43 of 99 NXP Semiconductors LPC15xx 32-bit ARM Cortex-M3 microcontroller 8.31 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 48-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 8.31.1 Features • 48-bit counter running from the main clock. Counter can be free-running or can be reset when an RIT interrupt is generated. • 48-bit compare value. • 48-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This allows for combinations not possible with a simple compare. 8.32 System tick timer The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval (typically 10 ms). 8.33 Real-Time Clock (RTC) The RTC resides in a separate, always-on voltage domain with battery back-up. The RTC uses an independent 32 kHz oscillator, also located in the always-on voltage domain. 8.33.1 Features • 32-bit, 1 Hz RTC counter and associated match register for alarm generation. • Separate 16-bit high-resolution/wake-up timer clocked at 1 kHz for 1 ms resolution with a more that one minute maximum time-out period. • RTC alarm and high-resolution/wake-up timer time-out each generate independent interrupt requests. Either time-out can wake up the part from any of the low power modes, including Deep power-down. |
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