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C8051F300-GS Datasheet(PDF) 76 Page - Silicon Laboratories |
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C8051F300-GS Datasheet(HTML) 76 Page - Silicon Laboratories |
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76 / 179 page  C8051F300/1/2/3/4/5 76 Rev. 2.9 SFR Definition 8.8. Bits7–6: UNUSED. Read = 11b, Write = don't care. Bit5: PT2: Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupt. 0: Timer 2 interrupts set to low priority level. 1: Timer 2 interrupts set to high priority level. Bit4: PS0: UART0 Interrupt Priority Control. This bit sets the priority of the UART0 interrupt. 0: UART0 interrupts set to low priority level. 1: UART0 interrupts set to high priority level. Bit3: PT1: Timer 1 Interrupt Priority Control. This bit sets the priority of the Timer 1 interrupt. 0: Timer 1 interrupts set to low priority level. 1: Timer 1 interrupts set to high priority level. Bit2: PX1: External Interrupt 1 Priority Control. This bit sets the priority of the External Interrupt 1 interrupt. 0: External Interrupt 1 set to low priority level. 1: External Interrupt 1 set to high priority level. Bit1: PT0: Timer 0 Interrupt Priority Control. This bit sets the priority of the Timer 0 interrupt. 0: Timer 0 interrupts set to low priority level. 1: Timer 0 interrupts set to high priority level. Bit0: PX0: External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value — — PT2 PS0 PT1 PX1 PT0 PX0 11000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) 0xB8 IP: Interrupt Priority |
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