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C8051F832-GS Datasheet(PDF) 10 Page - Silicon Laboratories |
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C8051F832-GS Datasheet(HTML) 10 Page - Silicon Laboratories |
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10 / 251 page  C8051F80x-83x 10 Rev. 1.0 Figure 13.1. CS0 Block Diagram ............................................................................. 71 Figure 13.2. Auto-Scan Example ............................................................................. 73 Figure 13.3. CS0 Multiplexer Block Diagram ........................................................... 80 14. CIP-51 Microcontroller Figure 14.1. CIP-51 Block Diagram ......................................................................... 82 15. Memory Organization Figure 15.1. C8051F80x-83x Memory Map ............................................................. 92 Figure 15.2. Flash Program Memory Map ............................................................... 93 16. In-System Device Identification 17. Special Function Registers 18. Interrupts 19. Flash Memory 20. Power Management Modes 21. Reset Sources Figure 21.1. Reset Sources ................................................................................... 123 Figure 21.2. Power-On and VDD Monitor Reset Timing ....................................... 124 22. Oscillators and Clock Selection Figure 22.1. Oscillator Options .............................................................................. 129 Figure 22.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 136 23. Port Input/Output Figure 23.1. Port I/O Functional Block Diagram .................................................... 138 Figure 23.2. Port I/O Cell Block Diagram .............................................................. 139 Figure 23.3. Port I/O Overdrive Current ................................................................ 140 Figure 23.4. Priority Crossbar Decoder Potential Pin Assignments ...................... 144 Figure 23.5. Priority Crossbar Decoder Example 1—No Skipped Pins ................. 145 Figure 23.6. Priority Crossbar Decoder Example 2—Skipping Pins ...................... 146 24. Cyclic Redundancy Check Unit (CRC0) Figure 24.1. CRC0 Block Diagram ........................................................................ 159 25. Enhanced Serial Peripheral Interface (SPI0) Figure 25.1. SPI Block Diagram ............................................................................ 167 Figure 25.2. Multiple-Master Mode Connection Diagram ...................................... 169 Figure 25.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram 169 Figure 25.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram 170 Figure 25.5. Master Mode Data/Clock Timing ....................................................... 172 Figure 25.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 172 Figure 25.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 173 Figure 25.8. SPI Master Timing (CKPHA = 0) ....................................................... 177 Figure 25.9. SPI Master Timing (CKPHA = 1) ....................................................... 177 Figure 25.10. SPI Slave Timing (CKPHA = 0) ....................................................... 178 Figure 25.11. SPI Slave Timing (CKPHA = 1) ....................................................... 178 26. SMBus Figure 26.1. SMBus Block Diagram ...................................................................... 180 Figure 26.2. Typical SMBus Configuration ............................................................ 181 |
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