NCP3218 datasheet(5/35 Pages) ONSEMI

Part #	NCP3218

Description	7-Bit, Programmable, 3-Phase, Mobile CPU Synchronous Buck Controller

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Manufacturer	ONSEMI [ON Semiconductor]

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ADP3212, NCP3218, NCP3218G

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5

ELECTRICAL CHARACTERISTICS

VCC = PVCC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V,

VVID = VDAC = 1.2000 V, TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign.

Parameter

Symbol

Conditions

Min

Typ

Max

Units

VOLTAGE CONTROL

VOLTAGE ERROR AMPLIFIER (VEAMP)

FB, LLINE Voltage Range (Note 2)

VFB, VLLINE

Relative to CSREF = VDAC

−200

+200

mV

FB, LLINE Offset Voltage (Note 2)

VOSVEA

Relative to CSREF = VDAC

−0.5

+0.5

mV

LLINE Bias Current

ILLINE

−100

+100

nA

FB Bias Current

IFB

−1.0

+1.0

mA

LLINE Positioning Accuracy

VFB − VVID

Measured on FB relative to VVID,

LLINE forced 80 mV below CSREF

−77.5

−80

−82.5

mV

COMP Voltage Range (Note 2)

VCOMP

0.85

4.0

V

COMP Current

ICOMP

COMP = 2.0 V, CSREF = VDAC

FB forced 200 mV below CSREF

FB forced 200 mV above CSREF

−0.75

6

mA

COMP Slew Rate

SRCOMP

CCOMP = 10 pF, CSREF = VDAC,

Open loop configuration

FB forced 200 mV below CSREF

FB forced 200 mV above CSREF

15

−20

V/ms

Gain Bandwidth (Note 2)

GBW

Non−inverting unit gain configuration,

RFB = 1 kW

20

MHz

VID DAC VOLTAGE REFERENCE

VDAC Voltage Range (Note 2)

See VID table

0

1.5

V

VDAC Accuracy

VFB − VVID

Measured on FB (includes offset),

relative to VVID

VVID = 1.2000 V to 1.5000 V,

T = −40°C to 100°C

VVID = 0.3000 V to 1.1875 V,

T = −40°C to 100°C

−8.5

−7.5

+8.5

+7.5

mV

VDAC Differential Non−linearity

(Note 2)

−1.0

+1.0

LSB

VDAC Line Regulation

ΔVFB

VCC = 4.75 V to 5.25 V

0.02

%

VDAC Boot Voltage

(ADP3212, NCP3218)

VBOOTFB

Measured during boot delay period

1.100

V

VDAC Boot Voltage (NCP3218G)

VBOOTFB

Measured during boot delay period

987.5

mV

Soft−Start Delay (Note 2)

tDSS

Measured from EN pos edge to

FB = 50 mV

200

ms

Soft−Start Time

tSS

Measured from FB = 50 mV to FB

settles to 1.1 V within 5%

1.4

ms

Boot Delay

tBOOT

Measured from FB settling to 1.1 V

within 5% to CLKEN neg edge

60

ms

VDAC Slew Rate (Note 2)

Soft−Start

Non−LSB VID step, DPRSLP = H,

Slow C4 Entry/Exit

Non−LSB VID step, DPRSLP = L,

Fast C4 Exit

LSB VID step, DVID transition

0.0625

0.25

1.0

0.4

LSB/ms

FBRTN Current

IFBRTN

−90

−200

mA

VOLTAGE MONITORING and PROTECTION

POWER GOOD

CSREF Undervoltage Threshold

VUVCSREF

Relative to nominal VDAC voltage

−240

−300

−360

mV

CSREF Overvoltage Threshold

VOVCSREF

Relative to nominal VDAC voltage

150

200

250

mV

CSREF Crowbar Voltage

Threshold

VCBCSREF

Relative to FBRTN, VVID > 1.1 V

Relative to FBRTN, VVID ≤ 1.1 V

1.5

1.3

1.55

1.35

1.6

1.4

V

1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2. Guaranteed by design or bench characterization, not production tested.

3. Based on bench characterization data.

4. Timing is referenced to the 90% and 10% points, unless otherwise noted.

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