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PL1084-1.8J3 Datasheet(PDF) 4 Page - Cystech Electonics Corp. |
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PL1084-1.8J3 Datasheet(HTML) 4 Page - Cystech Electonics Corp. |
4 / 6 page CYStech Electronics Corp. Spec. No. : C512J3 Issued Date : 2007.07.04 Revised Date : Page No. : 4/6 PL1084-XXXJ3 CYStek Product Specification Load Regulation Since the PL1084 is only a 3 terminal device, it is not possible to provide true remote sensing of output voltage at the load. The best load regulation is achieved when the bottom side of R2 is connected to the load and the top side of R1 is connected directly to the case or the Vout pin of the regulator and not to the load. It is important to note that for high current applications, this can represent a significant percentage of the overall load regulation and one must keep the path from the regulator to the load as short as possible to minimize this effect. Stability The PL1084 requires the use of an output capacitor as part of the frequency compensation in order to make the regulator stable. For most applications, a minimum of 10μF aluminum electrolytic capacitor insures both stability and good transient response. Thermal Design The PL1084 incorporates an internal shutdown that protects the device when the junction temperature exceeds the maximum allowable junction temperature. Although this device can operate with junction temperatures in the range of 150℃, it is recommended that the selected heat sink be chosen such that during maximum continuous load operation, the junction temperature is kept below the temperature. Layout Consideration The output capacitors must be located as close to the Vout terminal of the device as possible. It is recommended to use a section of a layer of the PC board as a plane to connect the Vout pin to the output capacitors to prevent any high frequency oscillation that may result due to excess trace inductance. |
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