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EPM3128A Datasheet(PDF) 3 Page - Altera Corporation |
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EPM3128A Datasheet(HTML) 3 Page - Altera Corporation |
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3 / 46 page  Altera Corporation 3 MAX 3000A Programmable Logic Device Family Data Sheet The MAX 3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high–density small-scale integration (SSI), medium-scale integration (MSI), and large-scale integration (LSI) logic functions. The MAX 3000A architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 3000A devices are available in a wide range of packages, including PLCC, PQFP, and TQFP packages. See Table 3. Note: (1) When the IEEE Std. 1149.1 (JTAG) interface is used for in–system programming or boundary–scan testing, four I/O pins become JTAG pins. MAX 3000A devices use CMOS EEPROM cells to implement logic functions. The user–configurable MAX 3000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debugging cycles, and can be programmed and erased up to 100 times. Table 2. MAX 3000A Speed Grades Device Speed Grade –4 –5 –6 –7 –10 EPM3032A vv v EPM3064A vv v EPM3128A vv v EPM3256A vv EPM3512A vv Table 3. MAX 3000A Maximum User I/O Pins Note (1) Device 44–Pin PLCC 44–Pin TQFP 100–Pin TQFP 144–Pin TQFP 208–Pin PQFP 256-Pin FineLine BGA EPM3032A 34 34 EPM3064A 34 34 66 EPM3128A 80 96 98 EPM3256A 116 158 161 EPM3512A 172 208 |
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