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EPM7160E Datasheet(PDF) 35 Page - Altera Corporation |
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EPM7160E Datasheet(HTML) 35 Page - Altera Corporation |
35 / 66 page Altera Corporation 35 MAX 7000 Programmable Logic Device Family Data Sheet Table 23. MAX 7000 & MAX 7000E External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit MAX 7000E (-12P) MAX 7000 (-12) MAX 7000E (-12) Min Max Min Max tPD1 Input to non-registered output C1 = 35 pF 12.0 12.0 ns tPD2 I/O input to non-registered output C1 = 35 pF 12.0 12.0 ns tSU Global clock setup time 7.0 10.0 ns tH Global clock hold time 0.0 0.0 ns tFSU Global clock setup time of fast input (2) 3.0 3.0 ns tFH Global clock hold time of fast input (2) 0.0 0.0 ns tCO1 Global clock to output delay C1 = 35 pF 6.0 6.0 ns tCH Global clock high time 4.0 4.0 ns tCL Global clock low time 4.0 4.0 ns tASU Array clock setup time 3.0 4.0 ns tAH Array clock hold time 4.0 4.0 ns tACO1 Array clock to output delay C1 = 35 pF 12.0 12.0 ns tACH Array clock high time 5.0 5.0 ns tACL Array clock low time 5.0 5.0 ns tCPPW Minimum pulse width for clear and preset (3) 5.0 5.0 ns tODH Output data hold time after clock C1 = 35 pF (4) 1.0 1.0 ns tCNT Minimum global clock period 11.0 11.0 ns fCNT Maximum internal global clock frequency (5) 90.9 90.9 MHz tACNT Minimum array clock period 11.0 11.0 ns fACNT Maximum internal array clock frequency (5) 90.9 90.9 MHz fMAX Maximum clock frequency (6) 125.0 125.0 MHz |
Similar Part No. - EPM7160E |
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Similar Description - EPM7160E |
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