ICS854104 datasheet(1/15 Pages) IDT

Part #	ICS854104

Description	Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

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Manufacturer	IDT [Integrated Device Technology]

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DATA SHEET

ICS854104AG REVISION A AUGUST 14, 2009

1

Low Skew, 1-to-4,

Differential-to-LVDS Fanout Buffer

ICS854104

General Description

The ICS854104 is a low skew, high performance

1-to-4 Differential-to-LVDS Clock Fanout Buffer and a

member of the HiPerClockS™ family of High

Performance Clock Solutions from IDT. Utilizing Low

Voltage Differential Signaling (LVDS), the ICS854104

provides a low power, low noise, solution for distributing clock signals

over controlled impedances of 100

Ω. The ICS854104 accepts a

differential input level and translates it to LVDS output levels.

Guaranteed output and part-to-part skew characteristics make the

ICS854104 ideal for those applications demanding well defined

performance and repeatability.

Features

• Four differential LVDS output pairs

• One differential clock input pair

• CLK/nCLK can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, HCSL, SSTL

• Each output has an individual OE control

• Maximum output frequency: 700MHz

• Translates differential input signals to LVDS levels

• Additive phase jitter, RMS: 0.232ps (typical)

• Output skew: 50ps (maximum)

• Part-to-part skew: 350ps (maximum)

• Propagation delay: 1.3ns (maximum)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

HiPerClockS™

ICS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

Q0

nQ0

Q1

nQ1

Q2

nQ2

Q3

nQ3

OE3

nCLK

CLK

GND

VDD

OE2

OE1

OE0

Q0

nQ0

Q1

nQ1

Q2

nQ2

Q3

nQ3

CLK

OE2

OE3

OE1

OE0

nCLK

Pulldown

Pullup/Pulldown

Pullup

Pin Assignment

ICS854104

16-Lead TSSOP

4.4mm x 5.0mm x 0.925mm package body

G Package

Top View

Block Diagram

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