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IDT7006SL Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT7006SL Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 20 page OCTOBER 2008 1 ©2008 Integrated Device Technology, Inc. DSC- 2739/16 IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM Features ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ High-speed access – Military: 20/25/35/55/70ns (max.) – Industrial: 55ns (max.) – Commercial: 15/17/20/25/35/55ns (max.) ◆ Low-power operation – IDT7006S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7006L Active: 700mW (typ.) Standby: 1mW (typ.) ◆ IDT7006 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device ◆ M/ S = H for BUSY output flag on Master, M/ S = L for BUSY input on Slave ◆ Busy and Interrupt Flags ◆ On-chip port arbitration logic ◆ Full on-chip hardware support of semaphore signaling between ports ◆ Fully asynchronous operation from either port ◆ Devices are capable of withstanding greater than 2001V electrostatic discharge ◆ Battery backup operation—2V data retention ◆ TTL-compatible, single 5V (±10%) power supply ◆ Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin TQFP ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Green parts available, see ordering information Functional Block Diagram I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/ WL CEL OEL BUSYL A13L A0L 2739 drw 01 I/O0L-I/O7L CEL OEL R/ WL SEML INTL M/S BUSYR I/O0R-I/O7R A13R A0R SEMR INTR CER OER (2) (1,2) (1,2) (2) R/ WR CER OER R/ WR 14 14 NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. |
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