Integrated Silicon Solution, Inc. — www.issi.com

1

Rev.A

10/17/2012

IS42S32200L

IS45S32200L

Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-

pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon

Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

FEATURES

• Clockfrequency:200,166,143,133MHz

• Fullysynchronous;allsignalsreferencedtoa

positive clock edge

• Internalbankforhidingrowaccess/precharge

• Single3.3Vpowersupply

• LVTTLinterface

• Programmableburstlength:

(1,2,4,8,fullpage)

• Programmableburstsequence:

Sequential/Interleave

• Selfrefreshmodes

• 4096refreshcyclesevery16ms(A2grade)or

64ms(Commercia,Industrial,A1grade)

• Randomcolumnaddresseveryclockcycle

• ProgrammableCASlatency(2,3clocks)

• Burstread/writeandburstread/singlewrite

operations capability

• Burstterminationbyburststopandprecharge

command

OPTIONS

• Packages:

86-pinTSOP-II

90-ballTF-BGA

• Operatingtemperaturerange:

OVERVIEW

organizedas524,288bitsx32-bitx4-bankforimproved

performance.ThesynchronousDRAMsachievehigh-speed

data transfer using pipeline architecture. All inputs and

outputs signals refer to the rising edge of the clock input.

512K Bits x 32 Bits x 4 Banks (64-MBIT)

SYNCHRONOUS DYNAMIC RAM

OCTOBER 2012

KEY TIMING PARAMETERS

Parameter

-5

-6

-7

Unit

ClkCycleTime

CAS

Latency=3

5

6

7

ns

CAS

Latency=2

7.5 7.5

7.5

ns

ClkFrequency

CAS

Latency=3

200 166 143

Mhz

CAS

Latency=2

133 133 133

Mhz

AccessTimefromClock

CAS

Latency=3

4.8 5.4

5.4

ns

CAS

Latency=2

5.4 5.4

5.4

ns