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C8051F124-GQR Datasheet(PDF) 80 Page - Silicon Laboratories

Part # C8051F124-GQR
Description  Mixed Signal ISP Flash MCU Family
Download  350 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F124-GQR Datasheet(HTML) 80 Page - Silicon Laboratories

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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
80
Rev. 1.4
SFR Definition 6.3. ADC0CF: ADC0 Configuration
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC
refers to the 5-bit value held in AD0SC4-0, and CLKSAR0 refers to the desired ADC0
SAR clock (Note: the ADC0 SAR Conversion Clock should be less than or equal to
2.5 MHz).
When the AD0SC bits are equal to 00000b, the SAR Conversion clock is equal to SYSCLK
to facilitate faster ADC conversions at slower SYSCLK speeds.
Bits2–0: AMP0GN2–0: ADC0 Internal Amplifier Gain (PGA).
000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
11x: Gain = 0.5
SFR Page:
SFR Address:
0
0xBC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
AD0SC4
AD0SC3
AD0SC2
AD0SC1
AD0SC0 AMP0GN2 AMP0GN1 AMP0GN0 11111000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
AD0SC
SYSCLK
2
C
 LK
SAR0
--------------------------------
1
=
AD0SC
00000b



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