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C8051F124-GQR Datasheet(PDF) 91 Page - Silicon Laboratories

Part # C8051F124-GQR
Description  Mixed Signal ISP Flash MCU Family
Download  350 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F124-GQR Datasheet(HTML) 91 Page - Silicon Laboratories

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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Rev. 1.4
91
7.
ADC2 (8-Bit ADC, C8051F12x Only)
The C8051F12x devices include a second ADC peripheral (ADC2), which consists of an 8-channel, config-
urable analog multiplexer, a programmable gain amplifier, and a 500 ksps, 8-bit successive-approximation-
register ADC with integrated track-and-hold (see block diagram in Figure 7.1). ADC2 is fully configurable
under software control via the Special Function Registers shown in Figure 7.1. The ADC2 subsystem (8-bit
ADC, track-and-hold and PGA) is enabled only when the AD2EN bit in the ADC2 Control register
(ADC2CN) is set to logic 1. The ADC2 subsystem is in low power shutdown when this bit is logic 0. The
voltage reference used by ADC2 is selected as described in Section “9. Voltage Reference” on
page 113
.
Figure 7.1. ADC2 Functional Block Diagram
7.1.
Analog Multiplexer and PGA
Eight ADC2 channels are available for measurement, as selected by the AMX2SL register (see SFR Defi-
nition 7.2). The PGA amplifies the ADC2 output signal by an amount determined by the states of the
AMP2GN2-0 bits in the ADC2 Configuration register, ADC2CF (SFR Definition 7.3). The PGA can be soft-
ware-programmed for gains of 0.5, 1, 2, or 4. Gain defaults to 0.5 on reset.
Important Note
: AIN2 pins also function as Port 1 I/O pins, and must be configured as analog inputs when
used as ADC2 inputs. To configure an AIN2 pin for analog input, set to ‘0’ the corresponding bit in register
P1MDIN. Port 1 pins selected as analog inputs are skipped by the Digital I/O Crossbar. See Section
“18.1.5. Configuring Port 1 Pins as Analog Inputs” on page 240
for more information on configuring
the AIN2 pins.
8-Bit
SAR
ADC
+
-
AV+
8
AV+
AD2EN
X
AGND
ADC2CF
AMX2SL
ADC2CN
Start Conversion
Timer 3 Overflow
Timer 2 Overflow
000
001
010
011
Write to AD2BUSY
CNVSTR2
1xx
Write to AD0BUSY
(synchronized with
ADC0)
8-to-1
AMUX
AIN2.0 (P1.0)
AIN2.1 (P1.1)
AIN2.2 (P1.2)
AIN2.3 (P1.3)
AIN2.4 (P1.4)
AIN2.5 (P1.5)
AIN2.6 (P1.6)
AIN2.7 (P1.7)
+
-
+
-
+
-
+
-
AMX2CF
ADC2LTH
ADC2GTH
16
Dig
Comp
AD2WINT
8
8


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