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C8051F124-GQR Datasheet(PDF) 94 Page - Silicon Laboratories |
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C8051F124-GQR Datasheet(HTML) 94 Page - Silicon Laboratories |
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94 / 350 page  C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 94 Rev. 1.4 7.2.3. Settling Time Requirements A minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the ADC2 MUX resistance, the ADC2 sampling capacitance, any external source resis- tance, and the accuracy required for the conversion. Figure 7.3 shows the equivalent ADC2 input circuit. The required ADC2 settling time for a given settling accuracy (SA) may be approximated by Equation 7.1. Note: An absolute minimum settling time of 800 ns required after any MUX selection. In low-power tracking mode, three SAR2 clocks are used for tracking at the start of every conversion. For most applications, these three SAR2 clocks will meet the tracking requirements. Equation 7.1. ADC2 Settling Time Requirements Where: SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB) t is the required settling time in seconds RTOTAL is the sum of the ADC2 MUX resistance and any external source resistance. n is the ADC resolution in bits (8). Figure 7.3. ADC2 Equivalent Input Circuit t 2 n SA ------- R TOTALCSAMPLE ln = R MUX = 5k RC Input= RMUX * CSAMPLE R MUX = 5k C SAMPLE = 5pF C SAMPLE = 5pF MUX Select MUX Select Differential Mode AIN2.x AIN2.y R MUX = 5k C SAMPLE = 5pF RC Input= RMUX * CSAMPLE MUX Select Single-Ended Mode AIN2.x Note: When the PGA gain is set to 0.5, C SAMPLE = 3pF |
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