![]() |
Electronic Components Datasheet Search |
|
C8051F124-GQR Datasheet(PDF) 97 Page - Silicon Laboratories |
|
C8051F124-GQR Datasheet(HTML) 97 Page - Silicon Laboratories |
97 / 350 page ![]() C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Rev. 1.4 97 SFR Definition 7.3. ADC2CF: ADC2 Configuration Bits7–3: AD2SC4–0: ADC2 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD2SC refers to the 5-bit value held in AD2SC4–0, and CLKSAR2 refers to the desired ADC2 SAR clock (Note: the ADC2 SAR Conversion Clock should be less than or equal to 6MHz). Bit2: UNUSED. Read = 0b; Write = don’t care. Bits1–0: AMP2GN1–0: ADC2 Internal Amplifier Gain (PGA). 00: Gain = 0.5 01: Gain = 1 10: Gain = 2 11: Gain = 4 SFR Page: SFR Address: 2 0xBC R/W R/W R/W R/W R/W R/W R/W R/W Reset Value AD2SC4 AD2SC3 AD2SC2 AD2SC1 AD2SC0 - AMP2GN1 AMP2GN0 11111000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 AD2SC SYSCLK CLK SAR2 ----------------------- 1 – = |
Similar Part No. - C8051F124-GQR |
|
Similar Description - C8051F124-GQR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |