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C8051F124-GQR Datasheet(PDF) 22 Page - Silicon Laboratories

Part No. C8051F124-GQR
Description  Mixed Signal ISP Flash MCU Family
Download  350 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F124-GQR Datasheet(HTML) 22 Page - Silicon Laboratories

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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
22
Rev. 1.4
Figure 1.2. C8051F121/125 Block Diagram
P0, P1,
P2, P3
Latches
JTAG
Logic
TCK
TMS
TDI
TDO
UART1
SMBus
SPI Bus
PCA
VDD
Monitor
Timers 0,
1, 2, 4
Timer 3/
RTC
P0
Drv
C
R
O
S
S
B
A
R
Port I/O
Config.
Crossbar
Config.
AV+
VDD
VDD
VDD
DGND
DGND
DGND
AGND
Reset
RST
Digital Power
Analog Power
Debug HW
Boundary Scan
P2.0
P2.7
P1.0/AIN2.0
P1.7/AIN2.7
P0.0
P0.7
P1
Drv
P2
Drv
Data Bus
Address Bus
Bus Control
DAC1
DAC1
(12-Bit)
VREF
DAC0
(12-Bit)
ADC
100 ksps
(12-Bit)
A
M
U
X
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
DAC0
CP0+
CP0-
CP1+
CP1-
VREF
TEMP
SENSOR
UART0
P3.0
P3.7
P3
Drv
8:1
MONEN
WDT
VREFA
Prog
Gain
CP0
CP1
C
T
L
P4 Latch
D
a
t
a
P7 Latch
A
d
d
r
P5 Latch
P6 Latch
P7
DRV
P5
DRV
P6
DRV
P4
DRV
Prog
Gain
ADC
500 ksps
(8-Bit)
A
M
U
X
VREFA
AV+
XTAL1
XTAL2
External Oscillator
Circuit
System
Clock
Calibrated Internal
Oscillator
PLL
Circuitry
128 kB
FLASH
256 byte
RAM
SFR Bus
8
0
5
1
C
o
r
e
8 kB
XRAM
External Data
Memory Bus
64x4 byte
cache


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