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C8051F124-GQR Datasheet(PDF) 27 Page - Silicon Laboratories

Part # C8051F124-GQR
Description  Mixed Signal ISP Flash MCU Family
Download  350 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F124-GQR Datasheet(HTML) 27 Page - Silicon Laboratories

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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Rev. 1.4
27
1.1.
CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F12x and C8051F13x utilize Silicon Labs’ proprietary CIP-51 microcontroller core. The CIP-51
is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can
be used to develop software. The core has all the peripherals included with a standard 8052, including five
16-bit counter/timers, two full-duplex UARTs, 256 bytes of internal RAM, 128 byte Special Function Regis-
ter (SFR) address space, and 8/4 byte-wide I/O Ports.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core exe-
cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
With the CIP-51's maximum system clock at 100 MHz, the C8051F120/1/2/3 and C8051F130/1/2/3 have a
peak throughput of 100 MIPS (the C8051F124/5/6/7 have a peak throughput of 50 MIPS).
Clocks to Execute
1
22/333/444/55
8
Number of Instructions
26
50
5
14
7
3
1
2
1


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