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C8051F124-GQR Datasheet(PDF) 30 Page - Silicon Laboratories

Part # C8051F124-GQR
Description  Mixed Signal ISP Flash MCU Family
Download  350 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F124-GQR Datasheet(HTML) 30 Page - Silicon Laboratories

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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
30
Rev. 1.4
1.3.
JTAG Debug and Boundary Scan
JTAG boundary scan and debug circuitry is included which provides non-intrusive, full speed, in-circuit
debugging using the production part installed in the end application, via the four-pin JTAG interface. The
JTAG port is fully compliant to IEEE 1149.1, providing full boundary scan for test and manufacturing pur-
poses.
Silicon Labs' debugging system supports inspection and modification of memory and registers, break-
points, watchpoints, a stack monitor, and single stepping. No additional target RAM, program memory, tim-
ers, or communications channels are required. All the digital and analog peripherals are functional and
work correctly while debugging. All the peripherals (except for the ADC and SMBus) are stalled when the
MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized.
The C8051F120DK development kit provides all the hardware and software necessary to develop applica-
tion code and perform in-circuit debugging with the C8051F12x or C8051F13x MCUs.
The kit includes a Windows (95 or later) development environment, a serial adapter for connecting to the
JTAG port, and a target application board with a C8051F120 MCU installed. All of the necessary commu-
nication cables and a wall-mount power supply are also supplied with the development kit. Silicon Labs’
debug environment is a vastly superior configuration for developing and debugging embedded applications
compared to standard MCU emulators, which use on-board "ICE Chips" and target cables and require the
MCU in the application board to be socketed. Silicon Labs' debug environment both increases ease of use
and preserves the performance of the precision, on-chip analog peripherals.
Figure 1.9. Development/In-System Debug Diagram
TARGET PCB
Serial
Adapter
JTAG (x4), VDD, GND
WINDOWS 95 OR LATER
Silicon Labs Integrated
Development Environment
C8051
F12x/13x


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