 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
C8051F124-GQR Datasheet(PDF) 35 Page - Silicon Laboratories |
|
||||||||||||||||||||||||||||||
C8051F124-GQR Datasheet(HTML) 35 Page - Silicon Laboratories |
|
|
35 / 350 page  C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Rev. 1.4 35 1.9. 8-Bit Analog to Digital Converter The C8051F12x devices have an on-board 8-bit SAR ADC (ADC2) with an 8-channel input multiplexer and programmable gain amplifier. This ADC features a 500 ksps maximum throughput and true 8-bit linearity with an INL of ±1LSB. Eight input pins are available for measurement. The ADC is under full control of the CIP-51 microcontroller via the Special Function Registers. The ADC2 voltage reference is selected between the analog power supply (AV+) and an external VREF pin. On the 100-pin TQFP devices, ADC2 has its own dedicated Voltage Reference input pin; on the 64-pin TQFP devices, ADC2 shares a Voltage Reference input pin with ADC0. User software may put ADC2 into shutdown mode to save power. A programmable gain amplifier follows the analog multiplexer. The gain stage can be especially useful when different ADC input channels have widely varied input voltage signals, or when it is necessary to "zoom in" on a signal with a large DC offset (in differential mode, a DAC could be used to provide the DC offset). The PGA gain can be set in software to 0.5, 1, 2, or 4. A flexible conversion scheduling system allows ADC2 conversions to be initiated by software commands, timer overflows, or an external input signal. ADC2 conversions may also be synchronized with ADC0 soft- ware-commanded conversions. Conversion completions are indicated by a status bit and an interrupt (if enabled), and the resulting 8-bit data word is latched into an SFR upon completion. Figure 1.14. 8-Bit ADC Diagram + - AV+ 8 8-to-1 AMUX X AIN2.0 AIN2.1 AIN2.2 AIN2.3 AIN2.4 AIN2.5 AIN2.6 AIN2.7 Configuration, Control, and Data Registers Programmable Gain Amplifier Analog Multiplexer 8-Bit SAR ADC Start Conversion Timer 3 Overflow Timer 2 Overflow Write to AD2BUSY CNVSTR2 Input Write to AD0BUSY (synchronized with ADC0) ADC Data Register Conversion Complete Interrupt External VREF Pin AV+ VREF Window Compare Logic Window Compare Interrupt |
Similar Part No. - C8051F124-GQR |
|
Similar Description - C8051F124-GQR |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
allmanual.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
