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C8051F124-GQR Datasheet(PDF) 37 Page - Silicon Laboratories |
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C8051F124-GQR Datasheet(HTML) 37 Page - Silicon Laboratories |
37 / 350 page ![]() C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Rev. 1.4 37 1.11. Analog Comparators Two analog comparators with dedicated input pins are included on-chip. The comparators have software programmable hysteresis and response time. Each comparator can generate an interrupt on a rising edge, falling edge, or both. The interrupts are capable of waking up the MCU from sleep mode, and Comparator 0 can be used as a reset source. The output state of the comparators can be polled in software or routed to Port I/O pins via the Crossbar. The comparators can be programmed to a low power shutdown mode when not in use. Figure 1.16. Comparator Block Diagram + - CPn+ CPn- CIP-51 and Interrupt Handler CPn CPn Output (Port I/O) SFR's (Data and Control) CROSSBAR 2 Comparators |
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