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BR24T32NUX-WG Datasheet(PDF) 3 Page - Rohm |
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BR24T32NUX-WG Datasheet(HTML) 3 Page - Rohm |
3 / 24 page Technical Note 3/21 BR24T□□□□Series www.rohm.com 2011.03 - Rev.A © 2011 ROHM Co., Ltd. All rights reserved. ●Action timing characteristics (Unless otherwise specified, Ta=-40~+85℃, VCC=1.7~5.5V) Parameter Symbol Limits Unit Min. Typ. Max. SCL frequency fSCL - - 400 kHz Data clock “HIGH“ time tHIGH 0.6 - - µs Data clock “LOW“ time tLOW 1.2 - - µs SDA, SCL rise time *1 tR - - 1.0 µs SDA, SCL fall time *1 tF - - 1.0 µs Start condition hold time tHD:STA 0.6 - - µs Start condition setup time tSU:STA 0.6 - - µs Input data hold time tHD:DAT 0 - - ns Input data setup time tSU:DAT 100 - - ns Output data delay time tPD 0.1 - 0.9 µs Output data hold time tDH 0.1 - - µs Stop condition setup time tSU:STO 0.6 - - µs Bus release time before transfer start tBUF 1.2 - - µs Internal write cycle time tWR - - 5 ms Noise removal valid period (SDA, SCL terminal) tI - - 0.1 µs WP hold time tHD:WP 1.0 - - µs WP setup time tSU:WP 0.1 - - µs WP valid time tHIGH:WP 1.0 - - µs *1 Not 100% TESTED. Condition Input data level:VIL=0.2×Vcc VIH=0.8×Vcc Input data timing refarence level: 0.3×Vcc/0.7×Vcc Output data timing refarence level: 0.3×Vcc/0.7×Vcc Rise/Fall time : ≦20ns ●Sync data input / output timing ○Input read at the rise edge of SCL ○Data output in sync with the fall of SCL Fig.1-(a) Sync data input / output timing Fig.1-(b) Start-stop bit timing Fig.1-(c) Write cycle timing Fig.1-(d) WP timing at write execution Fig.1-(e) WP timing at write cancel SCL SDA (input) SDA (output) tR tF tHIGH tSU:DAT tLOW tHD:DAT tDH tPD tBUF 70% 70% 30% 70% 70% 30% 30% 70% 70% 30% 70% 70% 70% 70% 30% 30% 30% 70% 70% tSU:STA tHD:STA START CONDITION tSU:STO STOP CONDITION 30% 30% 70% 70% D0 ACK tWR write data (n-th address) START CONDITION STOP CONDITION 70% 70% DATA(1) D0 ACK D1 DATA(n) ACK tWR 30% 70% STOP CONDITION tHD:WP tSU:WP 30% 70% DATA(1) D0 D1 ACK DATA(n) ACK tHIGH:WP 70% 70% tWR 70% |
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