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ADP3650 Datasheet(PDF) 1 Page - Analog Devices |
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ADP3650 Datasheet(HTML) 1 Page - Analog Devices |
1 / 12 page Dual, Bootstrapped, 12 V MOSFET Driver with Output Disable ADP3650 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved. FEATURES All-in-one synchronous buck driver Bootstrapped high-side drive One PWM signal generates both drives Anti-crossconduction protection circuitry OD for disabling the driver outputs APPLICATIONS Telecom and datacom networking Industrial and medical systems Point of load conversion: memory, DSP, FPGA, ASIC GENERAL DESCRIPTION The ADP3650 is a dual, high voltage MOSFET driver optimized for driving two N-channel MOSFETs, the two switches in a nonisolated synchronous buck power converter. Each driver is capable of driving a 3000 pF load with a 45 ns propagation delay and a 25 ns transition time. One of the drivers can be boot- strapped and is designed to handle the high voltage slew rate associated with floating high-side gate drivers. The ADP3650 includes overlapping drive protection to prevent shoot-through current in the external MOSFETs. The OD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdown. The ADP3650 is specified over the temperature range of −40°C to +85°C and is available in 8-lead SOIC_N and 8-lead LFCSP_VD packages. FUNCTIONAL BLOCK DIAGRAM 2 3 OD IN ADP3650 VCC BST DRVH SW DRVL PGND DELAY VCC 6 DELAY CMP CMP 1V 4 1 7 CONTROL LOGIC 6 5 8 RBST RG CBST1 D1 CBST2 12V Q1 TO INDUCTOR Q2 R1 LATCH R2 Q S Figure 1. |
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