 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
EP2AGX95EF29C6N Datasheet(PDF) 88 Page - Altera Corporation |
|
||||||||||||||||||||||||||||||
EP2AGX95EF29C6N Datasheet(HTML) 88 Page - Altera Corporation |
|
|
88 / 380 page  4–12 Chapter 4: DSP Blocks in Arria II Devices DSP Block Resource Descriptions Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation Pipeline Register Stage Figure 4–5 on page 4–8 shows that the output from the first-stage adder can either feed or bypass the pipeline registers. Pipeline registers increase the maximum performance (at the expense of extra cycles of latency) of the DSP block, especially when using the subsequent DSP block stages. Pipeline registers split up the long signal path between the input-registers/multiplier/first-stage adder and the second-stage adder/round-and-saturation/output-registers, creating two shorter paths. Second-Stage Adder There are four individual 44-bit second-stage adders per DSP block (two adders per half-DSP block). You can configure the second-stage adders as either: ■ The final stage of a 36-bit multiplier ■ A sum of four (18 × 18) ■ An accumulator (44-bits maximum) ■ A chained output summation (44-bits maximum) 1 You can use the chained-output adder at the same time as a second-level adder in chained output summation mode. The output of the second-stage adder has the option to go into the rounding and saturation logic unit or the output register. 1 You cannot use the second-stage adder independently from the multiplier and first-stage adder. Rounding and Saturation Stage Rounding and saturation logic units are located at the output of the 44-bit second-stage adder (the rounding logic unit followed by the saturation logic unit). There are two rounding and saturation logic units per half-DSP block. The input to the rounding and saturation logic unit can come from one of the following stages: ■ Output of the multiplier (independent multiply mode in 18 × 18) ■ Output of the first-stage adder (two-multiplier adder) ■ Output of the pipeline registers ■ Output of the second-stage adder (four-multiplier adder, multiply-accumulate mode in 18 × 18) These stages are described in “Arria II Operational Mode Descriptions” on page 4–14. The dynamic rounding and saturation signals control the rounding and saturation logic unit, respectively. A logic 1 value on the round signal, saturate signal, or both enables the round logic unit, saturate logic unit, or both. |
Similar Part No. - EP2AGX95EF29C6N |
|
Similar Description - EP2AGX95EF29C6N |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
