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EP2AGX65 Datasheet(PDF) 80 Page - Altera Corporation |
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EP2AGX65 Datasheet(HTML) 80 Page - Altera Corporation |
80 / 380 page 4–4 Chapter 4: DSP Blocks in Arria II Devices Simplified DSP Operation Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation Simplified DSP Operation In Arria II devices, the fundamental building block is a pair of 18 × 18-bit multipliers followed by a first-stage 37-bit addition and subtraction unit shown in Equation 4–1 and Figure 4–2. For all signed numbers, input and output data is represented in 2’s-complement format only. The structure shown in Figure 4–2 is useful for building more complex structures, such as complex multipliers and 36 × 36 multipliers, as described in later sections. Each Arria II DSP block contains four two-multiplier adder units (2 two-multiplier adder units per half block). Therefore, there are eight 18 × 18 multiplier functionalities per DSP block. For a detailed diagram of the DSP block, refer to Figure 4–5 on page 4–8. Following the two-multiplier adder units are the pipeline registers, the second-stage adders, and an output register stage. You can configure the second-stage adders to provide the alternative functions shown in Equation 4–1 and Equation 4–2 per half block. Equation 4–1. Multiplier Equation P[36..0] = A0[17..0] × B0[17..0] ± A1[17..0] × B1[17..0] Figure 4–2. Basic Two-Multiplier Adder Building Block DQ DQ A0[17..0] A1[17..0] B1[17..0] B0[17..0] P[36..0] +/- Equation 4–2. Four-Multiplier Adder Equation Z[37..0] = P0[36..0] + P1[36..0] |
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