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EP2AGX65 Datasheet(PDF) 85 Page - Altera Corporation |
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EP2AGX65 Datasheet(HTML) 85 Page - Altera Corporation |
85 / 380 page Chapter 4: DSP Blocks in Arria II Devices 4–9 DSP Block Resource Descriptions December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration Input Registers Figure 4–6 shows the input register of a half-DSP block. Figure 4–6. Input Register of Half-DSP Block (Note 1) Note to Figure 4–6: (1) The scanina signal originates from the previous DSP block, while the scanouta signal goes to the next DSP block. +/- +/- signa signb clock[3..0] ena[3..0] aclr[3..0] scanina[17..0] dataa_0[17..0] loopback datab_0[17..0] dataa_1[17..0] datab_1[17..0] dataa_2[17..0] datab_2[17..0] dataa_3[17..0] datab_3[17..0] scanouta Delay Register |
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