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EP2AGX65 Datasheet(PDF) 44 Page - Altera Corporation |
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EP2AGX65 Datasheet(HTML) 44 Page - Altera Corporation |
44 / 380 page 2–14 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices Adaptive Logic Modules Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation Shared Arithmetic Chain The shared arithmetic chain available in enhanced arithmetic mode allows the ALM to implement a 3-input add. This significantly reduces the resources necessary to implement large adder trees or correlator functions. The shared arithmetic chains can begin in either the first or sixth ALM in an LAB. The Quartus II Compiler creates shared arithmetic chains longer than 20 ALMs (10 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. To enhance fitting, a long shared arithmetic chain runs vertically, allowing fast horizontal connections to the TriMatrix memory and DSP blocks. A shared arithmetic chain can continue as far as a full column. Similar to the carry chains, the top and bottom half of shared arithmetic chains in alternate LAB columns can be bypassed. This capability allows the shared arithmetic chain to cascade through half of the ALMs in an LAB while leaving the other half available for narrower fan-in functionality. Every other LAB column is top-half bypassable, while the other LAB columns are bottom-half bypassable. 1 For more information on shared arithmetic chain interconnect, refer to “ALM Interconnects” on page 2–17. |
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