EP2AGX95 datasheet(45/380 Pages) ALTERA

Part #	EP2AGX95

Description	Device Interfaces and Integration

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Manufacturer	ALTERA [Altera Corporation]

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Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices

2–15

Adaptive Logic Modules

December 2010

Altera Corporation

Arria II Device Handbook Volume 1: Device Interfaces and Integration

LUT-Register Mode

LUT-Register mode allows third register capability in an ALM. Two internal feedback

loops allow combinational ALUT1 to implement the master latch and combinational

ALUT0

to implement the slave latch needed for the third register. The LUT register

shares its clock, clock enable, and asynchronous clear sources with the top dedicated

register. Figure 2–12 shows the register constructed using two combinational blocks in

the ALM.

Figure 2–13 shows the ALM in LUT-Register mode.

Figure 2–12. LUT Register from Two Combinational Blocks

4-input

LUT

5-input

LUT

clk

aclr

datain(datac)

sclr

sumout

Master latch

Slave latch

combout

LUT regout

sumout

combout

Figure 2–13. ALM in LUT-Register Mode with 3-Register Capability

datain

aclr

sclr

regout

latchout

datain

sdata

regout

aclr

datain

sdata

regout

aclr

DC1

E0

F1

E1

F0

clk [2..0] aclr [1..0]

reg_chain_in

lelocal 0

leout 0 a

leout 0 b

reg_chain_out

lelocal 1

leout 1 a

leout 1 b

Third register

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