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EP2AGX125 Datasheet(PDF) 48 Page - Altera Corporation |
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EP2AGX125 Datasheet(HTML) 48 Page - Altera Corporation |
48 / 380 page 2–18 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices Document Revision History Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation ■ Clocks represent a significant portion of dynamic power consumption due to their high switching activity and long paths. The LAB clock that distributes a clock signal to registers within an LAB is a significant contributor to overall clock power consumption. Each LAB’s clock and clock enable signal are linked. For example, a combinational ALUT or register in a particular LAB using the labclk1 signal also uses the labclkena1 signal. To disable an LAB-wide clock power consumption without disabling the entire clock tree, use the LAB-wide clock enable to gate the LAB-wide clock. The Quartus II software automatically promotes register-level clock enable signals to the LAB-level. All registers within the LAB that share a common clock and clock enable are controlled by a shared, gated clock. To take advantage of these clock enables, use a clock-enable construct in your HDL code for the registered logic. f For more information about implementing static and dynamic power consumption within the LAB, refer to the Power Optimization chapter in volume 2 of the Quartus II Handbook. Document Revision History Table 2–1 lists the revision history for this document. Table 2–1. Document Revision History Date Version Changes December 2010 2.0 Updated for the Quartus II software version 10.1 release: ■ Added Arria II GZ device information. ■ Updated “Logic Array Blocks”, “LAB Interconnects”, “LAB Control Signals”, “Adaptive Logic Modules”, “ALM Operating Modes”, “Normal Mode” sections. ■ Added Figure 2–7 and Figure 2–8. ■ Added “LAB Power Management Techniques” section. June 2009 1.1 Updated Figure 2–6. February 2009 1.0 Initial Release. |
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