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EP2AGX125 Datasheet(PDF) 70 Page - Altera Corporation |
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EP2AGX125 Datasheet(HTML) 70 Page - Altera Corporation |
70 / 380 page 3–22 Chapter 3: Memory Blocks in Arria II Devices Design Considerations Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2011 Altera Corporation Figure 3–21 shows sample functional waveforms of same-port read-during-write behavior in new data mode. Figure 3–22 shows sample functional waveforms of same-port read-during-write behavior in old data mode. For MLABs, the output of the MLABs can only be set to don’t care in same-port read-during-write mode. In this mode, the output of the MLABs is unknown during a write cycle. There is a window near the falling edge of the clock during which the output is unknown. Prior to that window, “old data” is read out; after that window, “new data” is seen at the output. Figure 3–21. M9K and M144K Blocks Same Port Read-During Write: New Data Mode clk_a wrena rdena address 0A 0B byteena 01 10 00 11 data_a A123 B456 C789 DDDD EEEE FFFF q_a (asynch) XX23 B4XX XXXX DDDD EEEE FFFF Figure 3–22. M9K and M144K Blocks Same Port Read-During-Write: Old Data Mode clk_a wrena rdena address A0 A1 byteena 01 10 00 11 data_a A123 B456 C789 DDDD EEEE FFFF q_a (asynch) A0 (old data) A1(old data) DDDD EEEE B423 DoldDold23 |
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