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EP2AGX190 Datasheet(PDF) 47 Page - Altera Corporation |
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EP2AGX190 Datasheet(HTML) 47 Page - Altera Corporation |
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47 / 380 page  Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices 2–17 Adaptive Logic Modules December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration ALM Interconnects There are three dedicated paths between ALMs: Register Cascade, Carry-chain, and Shared Arithmetic chain. Arria II devices include an enhanced interconnect structure in LABs for routing shared arithmetic chains and carry chains for efficient arithmetic functions. The register chain connection allows the register output of one ALM to connect directly to the register input of the next ALM in the LAB for fast shift registers. These ALM-to-ALM connections bypass the local interconnect. Figure 2–15 shows the shared arithmetic chain, carry chain, and register chain interconnects. Clear and Preset Logic Control LAB-wide signals control the logic for the register‘s clear signal. The ALM directly supports an asynchronous clear function. You can achieve the register preset through the Quartus II software’s NOT-gate push-back logic option. Each LAB supports up to two clears. Arria II devices provide a device-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software enables this pin. This device-wide reset overrides all other control signals. LAB Power Management Techniques The following techniques are used to manage static and dynamic power consumption within the LAB: ■ The Quartus II software forces all adder inputs low when ALM adders are not in use to save AC power. ■ Arria II LABs operate in high-performance mode or low-power mode. The Quartus II software automatically chooses the appropriate mode for the LAB, based on the design, to optimize speed versus leakage trade-offs. Figure 2–15. Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects ALM 1 ALM 2 ALM 3 Carry chain & shared arithmetic chain routing to adjacent ALM Local interconnect Register chain routing to adjacent ALM's register input Local interconnect routing among ALMs in the LAB ALM 10 |
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