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EP2AGX190 Datasheet(PDF) 63 Page - Altera Corporation |
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EP2AGX190 Datasheet(HTML) 63 Page - Altera Corporation |
63 / 380 page Chapter 3: Memory Blocks in Arria II Devices 3–15 Memory Modes December 2011 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration Figure 3–15 shows timing waveforms for read and write operations in mixed-port mode with unregistered outputs. True Dual-Port Mode Arria II M9K and M144K blocks support true dual-port mode. Sometimes called bidirectional dual-port, this mode allows you to perform any combination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. True dual-port memory supports input and output clock mode in addition to the independent clock mode. Figure 3–16 shows the true dual-port RAM configuration. The widest bit configuration of the M9K and M144K blocks in true dual-port mode are: ■ M9K: 512 × 16-bit (or 512 × 18-bit with parity) ■ M144K: 4K × 32-bit (or 4K × 36-bit with parity) Wider configurations are unavailable because the number of output drivers is equivalent to the maximum bit width of the respective memory block. Because true dual-port RAM has outputs on two ports, its maximum width equals half of the total number of output drivers. Figure 3–15. Mixed-Port Read-During-Write Timing Waveforms clk_a wrena rdena address A0 A1 byteena 01 10 00 11 data_a A123 B456 C789 DDDD EEEE FFFF q_a (asynch) A0 (old data) A1(old data) DDDD EEEE B423 DoldDold23 Figure 3–16. Arria II True Dual-Port Memory data_a[ ] address_a[ ] wren_a byteena_a[] addressstall_a clock_a enable_a rden_a aclr_a q_a[] data_b[ ] address_b[] wren_b byteena_b[] addressstall_b clock_b enable_b rden_b aclr_b q_b[] |
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