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EP2AGX190 Datasheet(PDF) 36 Page - Altera Corporation |
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EP2AGX190 Datasheet(HTML) 36 Page - Altera Corporation |
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36 / 380 page  2–6 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices Adaptive Logic Modules Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation Figure 2–6 shows a detailed view of all the connections in an ALM. One ALM contains two programmable registers. Each register has data, clock, clock enable, synchronous and asynchronous clear, and synchronous load and clear inputs. Global signals, general purpose I/O (GPIO) pins, or any internal logic can drive the register’s clock and clear-control signals. Either GPIO pins or internal logic can drive the clock enable. For combinational functions, the register is bypassed and the output of the LUT drives directly to the outputs of an ALM. Each ALM has two sets of outputs that drive the local, row, and column routing resources. The LUT, adder, or register output can drive the ALM outputs (refer to Figure 2–6). For each set of output drivers, two ALM outputs can drive column, row, or direct link routing connections, and one of these ALM outputs can also drive local interconnect resources. The LUT or adder can drive one output while the register drives another output. Figure 2–6. Connection Details of the Arria II ALM D Q + reg_chain_in aclr[1:0] sclr syncload clk[2:0] carry_in dataf0 datae0 dataa datab datac1 datae1 dataf1 shared_arith_out carry_out reg_chain_out CLR D Q CLR shared_arith_in local interconnect row, column direct link routing row, column direct link routing local interconnect 4-INPUT LUT 4-INPUT LUT 3-INPUT LUT 3-INPUT LUT 3-INPUT LUT 3-INPUT LUT + datac0 VCC GND row, column direct link routing row, column direct link routing |
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